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Working as Director - ASIC Design at Alphawave Semi , talented with excellent employee development, customer service and analytics skills coupled with more than 23 years of experience. Comfortable giving engaging presentations to clients to drive new business, expand accounts and establish brand profile. Excellent team builder and leader of initiatives. Passionate about applying excellent organization and communication skills to manage and lead teams.
In Past, worked as SOC Design Engineering Manager at Intel India prior to Alphawave. Adept in complete closure of Physical Design (from RTL to GDS2) with added expertise in large Team Management. Expertise in driving complex projects to completion, managing large teams, and achieving SOC convergence. Skilled in PD, STA, DFT, DRC, Signal EM, IR analysis, etc and fostering a goal-oriented team environment, demonstrating exceptional leadership and technical prowess.
Encouraging manager and analytical problem-solver with talents for team building, leading and motivating, as well as excellent customer relations aptitude and relationship-building skills. Proficient in using independent decision-making skills and sound judgment to positively impact company success. Dedicated to applying training, monitoring and morale-building abilities to enhance employee engagement and boost performance.
Pursuing full-time role that presents professional challenges and leverages interpersonal skills, effective time management, and problem-solving expertise.


  Passionate Physical Design Engineer having 8+ years of experience in Chip Designing and has strong knowledge of the complete IC design cycle.
  Strong fundamentals in physical design execution through handling diverse blocks in multiple projects from 22nm- 90nm technology.
  Expertise in Designing and Implementation of Low Power Techniques in IC Design, Having full knowledge of Unified Power Format (UPF), CPF and Low power Implementation techniques to achieve lower consumption with better IC performance.
  Vastly works in IoT Domain with Designs having a lot of power domains ~150 and successfully achieved Industry the best Power Metrics.
  Certified as Low Power Implementation Designer in IoT ASIC's.
  Having Strong knowledge in Floorplanning, Macros placement, Power Planning and Physical Implementation with both Synopsys (Fusion Compiler, ICC2 Compiler) and Cadence (Encounter and Innovus) EDA tool sets.
  Expertise in Physical Implementation includes PnR, Clock Tree Synthesis(CTS), RC - Extraction with both Synopsys and Cadence tool sets
  Having Strong knowledge in timing closure with both Synopsys (Prime Time) and Cadence (Tempus) tool sets.
  Implemented lot of ECO's which are related to Timing and Design Rule Fixing.
  Having strong knowledge in Design Planning and Library Preparations includes Memory Generation from different Vendors, Constraint Development of blocks with various clocks.
  Strong knowledge in Front End Implementation of IC Design with both Synopsys (Fusion, Design Compiler) and Cadence (Genus) tools.
  Having Strong knowledge in various Front End Implementation checks includes Lint Checking, Clock Domain Crossings, Formal Verification and Low power checks with both Synopsys (Formality, VSI-LP) and Cadence (Conformal LEC and Conformal LP) tool sets.
  Strong knowledge in Implementation of different DFT modes (MBIST and SCAN) in the Design.
  Strong knowledge in device physics and research experience which focused on the design, Integration and Implementation of novel, digital on-chip voltage sensing schemes in nanometer CMOS.
  Strong knowledge in Physical Verification includes Design Rule Check(DRC), Layout vs Schematics (LVS), SignalEM, Electro Static Discharge(ESD), Electrical Rule Check (ERC) and power ramp-up analysis with Calibre tools.
  Expertise in execution and debugging Low Power issues like Dynamic/Static IR Drop and Power Network Improvements based on the IR Drop results with both Apache and Voltus Tools.
  Expertise in Scripting languages like Perl, TCL.
  Expertise in IoT Design Architecture with different Power Scenarios and clocks.
  Successfully Implemented lot of Low Power (Clock Gating, Power Gating and Dynamic Voltage Scaling) techniques to achieve best power metrics.
  Certified in VLSI Physical Design and Embedded Systems in 2016
  Having strong knowledge in Verilog, System Veriog Coding and having basic knowledge of UVM.
  Having Strong knowledge in different WIFI Protocols includes 802.11b, g, n, ah and ax, Having basic knowledge on Bluetooth protocol.
  Having Strong knowledge in C, C++, Data Structures and LINUX Programming.
  Expertise in Firmware Development, Strong knowledge on RTOS Concepts.
  Strong knowledge from Application to Hardware Communication.
  EDA Tools : Genus, Conformal LEC, Conformal LP, Encounter, Innovus, Tempus, Voltus, Calibre, Apache, Design Compiler, Test Compiler, Formality, VSI-LP, Fusion Compiler, ICC2 and Prime Time.


Seeking a position as Senior Design and Verification engineer which offers key participation, team-oriented tasks and
challenges that help in technical skill enhancement and also to become an asset to the organization by striving towards the attainment of its goals and hence valuably contribute to its success.

More than 4 years of enriched experience in Physical Design with multi-million gate design tape-outs.
Experience in leading Engineers in multiple projects.
Independent Execution of Synthesis, P&R (PnR) & all sign-off checks (STA, EMIR, LEC, LVS & DRC).
Expertise in Timing Analysis, Timing Closure & Advanced STA concepts.
Experience in Clock Spine Implementation for best latency and skew.
Expertise in Congestion Analysis and Clock Tree Synthesis.
Strong experience and knowledge in TCL, VIM & Unix.
Good knowledge in Synthesis, Floor Planning, Placement, Routing, EMIR, LEC and PV.

Maryam Nawaz

Summary

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Deputy Assistant Director

Teacher

Education

Msc (Masters) - Masters in Mathematics

Bachelors - Double Maths + Physics

Matric - Science Education

FSc (HSSC) - Engineering (Pre-Engineering)

Skills

Timeline

Deputy Assistant Director

Teacher

Msc (Masters) - Masters in Mathematics

Bachelors - Double Maths + Physics

FSc (HSSC) - Engineering (Pre-Engineering)

Matric - Science Education

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