Khan Salik Najeeb

I am currently Working as RTL Design Engineer. Here are some of my major Contributions.

• Accomplished design of 5 stage pipelined risc-v based processor.
• Implemented SoC based on above processor.
• Worked in depth on L1 instruction and data cache implemented all policies of cache and replacement schemes
• Integrated AXI bus in SoC .
• Connected multiple peripherals through wishbone interconnect.
• Worked on AXI interconnect in multiple master multiple slave configurations.
• Established compliance testing of processor.
• Modelling on verilator and Vivado .

I have hands on experience in RTI design from designing a module on hdl until its testing on FPGA boards ,its timing diagram timing closure and debugging through ILA core .