Design Verification Engineer
CoMira Solutions
10.2022 - Current
- Collaborated on UVM-based functional verification for D2D interconnect, worked on the constraint randomization of flits, virtual sequences for the link training process and retry mechanism, encompassing detailed test planning, development of reusable UVM components for VIP-to-VIP verification process, and creation of complex, constrained-random test scenarios. Managed simulation campaigns, performed in-depth debug of failures, and actively contributed to design bring-up and achievement of coverage objectives.
- Designed and implemented highly reusable and configurable UVM-based verification environments for AXI and APB bus protocols, significantly improving verification efficiency across multiple projects.
- Executed a detailed verification plan for a FIFO with an integrated ALU, performing UVM-based functional verification to ensure data integrity and control logic accuracy. Developed scoreboards and checkers for comprehensive end-to-end validation.
