Arhan Yaqub

• At Rapid Silicon, we believe that Open-Source technologies & platforms can empower individuals & organizations to challenge the status quo.
• Responsible for leading design & design verification teams from concept through to production for re-programmable System-on-Chip (SoC) solutions.
• Technical Lead for Design & Verification teams developing reprogrammable SoC with integrated PUF-based secure eFPGA IP and RISC-V processor for edge computing and industrial automation applications.
• Developed the verification strategy and planning for complex IPs highlighting LP/DDRx, SRAM, GBE, eFPGA configuration controller, and eFPGA IP in a subsystem and SoC using in-house and 3rd party UVCs (Universal Verification Components).
• Deployed Formal Verification techniques to verify the controller block and CSRs (control and status registers) generated through SytemRDL for PCIe IP.
• Successfully signed-off the full verification and prototyping of our first re-programmable SoC on 16nm FFT (TSMS).
• Train and coach the teams to efficiently utilize their potential and to meet demand supply imbalance in Semiconductors.
• Published the innovative work on "Comprehensive Verification Strategy for embedded eFPGA IP Integrated into PUF-based secure System-on-Chip" - SNUG Silicon Valley 2024.

• Sr. Mixed-Signal Design Verification Lead for an Automotive LiDAR sensing Mixed Signal Companion Chip project.
• Adeptly devised and executed the Verification plan using the Cadence vPlan tool, aligning it with project requirements.

Key Accomplishments:

• Developed a UVM-based testbench architecture tailored for the LiDar Analog Mixed-Signal (AMS) front-end companion chip consisting of 2D/3D solid-state LiDARs front-end for object detection in advanced driver assistance systems (ADAS) and autonomous driving (AD) applications.
• Modeled the behavior of transimpedance amplifiers (TIAs) and verified their configuration and controller block's functionality in UVM.
• Verified host interface serial protocols including I2C and SPI/SafeSPI, and seamlessly integrated Universal Verification Components (UVCs) into the UVM system-level testbench.
• Collaborated closely with Digital and Mixed-Signal design units, contributing to the specification, development, and debugging of test cases.
• Actively supported the generation of behavioral models for analog front-end components.
• Performed gate-level simulations with SDF back-annotation on the netlist, effectively resolving discrepancies.
• Seamlessly integrated the testbench environment with the System-in-Package (SiP) level, advancing the Main die's verification efforts.
• Developed scoreboard to model the functionality of various analog frontend die's components to be verified in main digital die.
• Demonstrated expertise in verifying the Functional Safety (FuSa) features of the LiDar System-on-Chip (SoC), adhering to ISO26262 standards.

• Engaged within the Automotive Micro-controller & Processors division, focusing on Project Verification.

Key Accomplishments:

• Served as the deputy lead for the Analog Mixed-Signal Companion Chip (ACD), tailored for automotive motor control applications.
• Conducted verification of on-chip interconnect protocols for the ARM-based multi-core MCU, including AXI, AHB, and APB, leveraging Synopsys VIPs.
• Designed and developed the JTAG UVM environment to validate JTAG functionality.
• Collaborated on verifying the MCU's on-chip peripherals.
• Worked closely with the DFT team to support and verify the SoC's Design for Testability (DFT) functionality.
• Contributed to the System-on-Chip (SoC) integration and verification of NXP's proprietary fast die-to-die Serial Communication Interface (DiPort), culminating in a successful chip tape-out for Automotive SoCs.
• Completed Functional Safety Management training for Automotive SoCs in accordance with ISO26262 standards.
• Undertook Formal Verification of clock connectivity and CDC to on-chip peripherals, while ensuring register connectivity checks of the MCU using the Cadence IFV (Incisive Formal Verifier) tool.
• Achieved essential 100% functional and code coverage targets using cover properties and cover-groups.
• Concluded by overseeing the sign-off process for the ACD tape-out following gate-level simulations and SDF timing analysis of the netlist.
• Executed verification cycles on a variety of digital designs, ranging from small blocks to large SoC's.
• Published the innovative work on "Implementation of an innovative Porthole Mechanism bridging the ARM Core Model (SystemC) and UVM testbench for the MCU using TLM2.0 protocol - SNUG Silicon Valley 2019.

A pivotal member of the PMIC (Power Management ICs) Digital Design group, contributing within a highly diverse and multicultural workspace comprising professionals from ten different nationalities.

Key Involvements:

• Design and verification of Digital & Mixed Signal IP Blocks, encompassing UART, LDO controller, and OTP controller blocks.
• Assumed responsibility as the proprietor of the OTP verification IP, leveraging constraint-random class-based environments and UVM libraries.
• Owned the PMIC control unit (MFSM/RFSM) verification IP, employing a combination of System Verilog Assertions (SVAs) and formal verification techniques.
• Developed SVA-based verification for managing CDC (Clock Domain Crossing) challenges in split-PMIC projects.
• Developed and provided support for utilities aimed at testbench and regression automation, boosting efficiency through Python and Perl scripting.
• Played a pivotal role in the core team tasked with designing a system-level class-based (UVM-lite) testbench environment tailored for split-PMIC projects.
• Executed comprehensive Functional & Code Coverage assessments for Digital IPs utilizing diverse verification methodologies.
• Skillfully devised verification plans using tools like vPlan and IEM eManager.
• Directed test-oriented verification strategies for Digital & Mixed Signal IP blocks.
• Implemented SVA-based verification for Digital IPs, encompassing LDO controllers, OTP Controllers, and MFSM units.
• Executed Formal Verification for Digital IPs (MFSM, LDO Controller, OTP Controller) utilizing Cadence Formal Verifier IFV tool.
• Demonstrated success in the tape-out of five PMIC projects, with four in active production and one serving as a test chip.
• Contributed as a DV (Design Verification) support engineer, collaborating on off-shore PMIC projects in coordination with Dialog's teams located in Swindon (UK) and Livorno (Italy).

Worked in Industrial robot manipulators Group

• Design and Implementation of Dynamic Manipulation for industrial robot manipulators.
• Comparison of control strategies for 6-DoF Robot ManipulatorDoF Robot Manipulator modeling using Matlab-Simulink
• PDI controller for basketball catching and balancing
• Computer vision algorithms optimization for trajectory planning
• Reactive and Sensor-Based Planning