Abdul Qadeer

Motivated and skilled RTL/FPGA Engineer with a solid background in Digital Design, Computer Architecture, and FPGA implementation. Experienced in developing Software-Defined Radio (SDR) based jamming solutions. Proficient in Verilog, RTL design, and Bash scripting, with hands-on experience in performance simulation of RISC-V–based designs using open-source tools such as Gem5 and Spike. Adept at system-level debugging, timing analysis, and hardware-software integration. Strong problem-solving skills with a passion for building efficient and scalable hardware solutions for complex digital systems.

• Design and Development of RISC-V Based Virtual Cluster using QEMU
• The physical cluster outperforms the virtual one by up to 50% in some cases. However, the virtual approach offers scalability, flexibility, and cost-effective HPC development & testing—a promising step for HPC, cloud computing, edge computing, and IoT applications.
• https://www.researchgate.net/publication/388139232_Design_and_Development_of_RISC-V_Based_Virtual_Cluster_using_QEMU_Simulator

• RTL Design & Verification (Verilog, SystemVerilog)
• FPGA Development & Prototyping (Xilinx Vivado)
• Digital Design
• Computer Architecture
• VLSI Design
• Software-Defined Radio (SDR) Systems & Jamming Solutions
• RISC-V Performance Simulation (Gem5, Spike)
• Bash Scripting & Linux-based Development
• Timing Analysis & System-Level Debugging
• Hardware-Software Co-Design

• English
• Urdu